The present invention relates generally to integrated circuit (IC) design, and more particularly to voltage level shifter designs.
In a deep submicron technology for a typical IC chip, device feature sizes, such as gate oxide thickness and channel length, have greatly reduced. In order to work with such small geography devices, the power supply voltage have to be lowered, otherwise the gate oxide may breakdown and the transistor channel may punch through. For instance, for a 90 nm technology, the power supply voltage is about 1.0V. However, in a system level, i.e., outside the IC chip, a power supply voltage may still be 2.5V or 3.3V. In order to allow such deep submicron IC chip to properly work in the high voltage system, voltage level shifters have to be employed to shift an external high voltage signal to a corresponding internal low voltage signal, and to shift an internal low voltage signal to a corresponding external high voltage signal.
FIG. 1 is a schematic diagram illustrating a conventional low-to-high voltage level shifter 100. The voltage level shifter 100 comprises a pair of PMOS transistors 112 and 116, a pair of NMOS transistors 122 and 126, and an inverter 130. These devices are connected as a cross-latch. Specifically, the PMOS transistor 112 and the NMOS transistor 122 are serially connected between an external power supply VCCH and a ground VSS, so are the PMOS transistor 116 and NMOS transistor 126. A gate of the PMOS transistor 112 is connected to the common drain of the PMOS transistor 116 and the NMOS transistor 126. A gate of the PMOS transistor 116 is connected to the common drain of the PMOS transistor 112 and the NMOS transistor 122. An input node IN is connected to a gate of the NMOS transistor 122, and to a gate of the NMOS transistor 126 through the inverter 130. An output node OUT is connected to the common drain of the PMOS transistor 116 and the NMOS transistor 126. A skilled in the art would immediately recognize that the voltage level shifter 100 functions as a two serially connected inverters from the input IN and output OUT point of view. For instance, when the input node IN is at a logic HIGH, the NMOS transistor 122 and the PMOS transistor 116 will be turned on, and the NMOS transistor 126 and the PMOS transistor 112 will be turned off, thus the output node OUT will be at the logic HIGH. However, the input node IN operates at an internal voltage between the VSS and a VCCL which is lower than the VCCH, while the output node OUT operates at an external voltage between the VSS and the VCCH. PMOS transistors 112 and 116 and NMOS transistors 122 and 126, exposing to the VCCH, are high voltage transistors with thick gate oxide, etc. The inverter 130, exposing only to the VCCL, is made of low voltage transistors with thin gate oxide, etc. With a proper adjustment of the threshold voltages of the NMOS transistors 122 and 126, the voltage level shifter 100 can achieve a voltage transition point around VCCL/2.
Referring again to FIG. 1, the node OUT achieves voltage level transition, like in an ordinary inverter, through on-and-off switching by the PMOS transistor 116 and the NMOS transistor 126. Specifically, assuming in a prior state, the node OUT is in a logic HIGH, then the PMOS transistor 116 is on, and the NMOS 126 transistor is off. In the new state, the node OUT turns to a logic LOW, then the PMOS transistor 116 is switched from on to off, and the NMOS transistor is switched from off to on. During the transition during, both the PMOS transistor 116 and the NMOS transistor 126 are on and one of the transistors fights against the transition. A successful transition depends on a proper balance of strength between the PMOS transistor 116 and the NMOS transistor 126. The same is true for the PMOS transistor 112 and the NMOS transistor 122. In the voltage level shifter 100, the voltage at the nodes IN and INB can only reach the VCCL, which cannot fully turns on or forcefully shut off the high voltage NMOS transistor 122 or 126. The lower the VCCL is, the weaker the NMOS transistor 122 or 126 is, and eventually the voltage level shifter 100 will fail to make the transition. Therefore, the poor strength of the NMOS transistors 122 and 126 is a bottleneck that limits how low the VCCL can go. Typically, the conventional voltage level shifter 100 can operate at 0.65V of the VCCL, when the VCCH is about 1.1V. However, some advanced IC systems require a proper working when the VCCL is as low as 0.4V, which cannot be achieved by the conventional voltage level shifter 100.
As such, what is desired is an improved voltage level shifter that can operate at the lower VCCL by overcoming the weakness in the NMOS transistors 122 and 126 of FIG. 1.